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NXP Semiconductors /LPC18xx /GPDMA /RAWINTERRSTAT

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Interpret as RAWINTERRSTAT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RAWINTERRSTAT0)RAWINTERRSTAT0 0 (RAWINTERRSTAT1)RAWINTERRSTAT1 0 (RAWINTERRSTAT2)RAWINTERRSTAT2 0 (RAWINTERRSTAT3)RAWINTERRSTAT3 0 (RAWINTERRSTAT4)RAWINTERRSTAT4 0 (RAWINTERRSTAT5)RAWINTERRSTAT5 0 (RAWINTERRSTAT6)RAWINTERRSTAT6 0 (RAWINTERRSTAT7)RAWINTERRSTAT7 0RESERVED

Description

DMA Raw Error Interrupt Status Register

Fields

RAWINTERRSTAT0

Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RAWINTERRSTAT1

Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RAWINTERRSTAT2

Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RAWINTERRSTAT3

Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RAWINTERRSTAT4

Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RAWINTERRSTAT5

Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RAWINTERRSTAT6

Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RAWINTERRSTAT7

Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
RESERVED

Reserved. Read undefined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data